1. Field of Invention
This invention relates in general to a planarization technique used in the manufacturing of integrated circuits. More particularly, this invention relates to a method of planarizing an inter-layer dielectric (ILD) layer.
2. Description of Related Art
In general, there are two types of dielectrics which are grouped under the title of inter-layer dielectric (ILD). The first type is a pre-metal dielectric (PMD), which refers generally to a dielectric material formed before a metallization process is performed. The PMD serves as an isolating layer located between a semiconductor component and a first metallic layer. The second type of dielectric is an inter-metal dielectric (lMD), which is a dielectric layer interposed between two metallic layers, and is used for isolation purposes.
FIG. 1a through 1c illustrate a conventional method of planarizing a PMD layer. First, and referring to FIG. 1a, a semiconductor substrate 10 having a field effect transistor (FET) 12 formed thereabove is provided. Thereafter, an undoped silicate glass (USG) layer 14 and a doped silicate glass layer 16 are formed, in sequence, above the semiconductor substrate 10. The undoped silicate glass layer 14 is formed, for example, using an atmospheric pressure chemical vapor deposition (APCVD) method, or a sub-atmospheric chemical vapor deposition (SACVD) method. The doped silicate glass layer 16 is composed from, for example, phosphosilicate glass (PSG) or borophosphosilicate glass (BPSG).
Referring next to FIG. 1b, a heat reflow operation is performed at a temperature of about 800.degree. C. to about 900.degree. C. As a result, the silicate glass layers 14 and 16 become denser, and obtain a smoother appearance.
Lastly, and referring to FIG. 1c, chemical-mechanical polishing (CMP) is used to planarize the doped silicate glass layer 16. Then, an oxide layer 18 is deposited thereabove using, for example, a plasma-enhanced chemical vapor deposition (PECVD) method (which forms a silicon dioxide layer). Alternatively, tetra-ethyl-ortho-silicate (TEOS) can be provided as the main reactive gas to form a silicon dioxide layer.
Before the performance of the operations shown in FIG. 1c, that is, immediately after CMP step, an oxide layer may first be deposited above the silicate glass layer 16. The oxide layer acts as a passivation layer for protecting the silicate glass layer 16 from the formation of void structure.
However, the conventional manufacturing process is complex and requires a high temperature to densify the silicate glass layers 14 and 16. Therefore, the known process is unsuitable for most logic circuit products, especially when the front end processes, in the manufacturing of integrated circuits, include self-aligned silicide processes. As such, planarization of the PMD layer cannot be achieved in this known manner. Additionally, when the silicate glass layer 16 is subjected to the CMP operation, the polishing rate and the uniformity of the layer is difficult to control.